1. Technical Field
Various embodiments generally relate to an integrated apparatus, and more particularly, to a flip-flop circuit and a semiconductor apparatus using the same.
2. Related Art
With the increase in capacity and integration degree of semiconductor memory apparatuses, it takes a lot of time to test a semiconductor memory apparatus. Thus, a scan test, a daisy chain test and the like, which are capable of improving test efficiency, may be mainly used.
In order to perform a scan test or daisy chain test, a circuit having flip-flops, for example, D flip-flops coupled in series may be installed in a memory apparatus. In some cases, tens of thousands of D flip-flops may be required for the test.
FIG. 1 is a circuit diagram of a conventional D flip-flop. Wherever possible, the same reference numbers will be used throughout the prior art drawings to refer to the same or like parts.
Referring to FIG. 1, the conventional D flip-flop 1 may have an input unit 11, a driving unit 13, an output unit 15, and a reset unit 17.
The input unit 11 is configured to receive data D in response to clock signals CLK and CLKB. The driving unit 13 is configured to delay a signal outputted through the input unit 11 by a predetermined time in response to the clock signals CLK and CLKB and a reset signal RST, and output the delayed signal. The output unit 15 is configured to output the output signal of the driving unit 13 as output data Q. The reset unit 17 is configured to reset the state of the D flip-flop 1. FIG. 1 also illustrates a power supply voltage VDD.
FIG. 2 illustrates an example of a D flip-flop chain circuit. Referring to FIG. 2, the D flip-flop chain circuit includes a plurality of D flip-flops, for example, n D flip-flops coupled in series (n being a natural number greater than zero).
A first D flip-flop DFF0 is configured to generate output data D1 in response to the reset signal RST, input data D0, and the clock signal CLK. A second D flip-flop DFF1 is configured to generate output data D2 (not shown) in response to the reset signal RST, the output signal D1 of the previous D flip-flop, and the clock signal CLK. Thus, generally speaking, an n-th D flip-flop is configured to generate output data Dn in response to the reset signal RST, an output signal Dn−1 of the previous D flip-flop Dn−1, and the clock signal CLK.
In the D flip-flop chain circuit of FIG. 2, the clock signal CLK is provided to each of the D flip-flops DFF0 to DFFn−1. Thus, the loading of the clock signal CLK inevitably increases.
Output data of flip-flops such as the D flip-flops are changed at a rising or falling edge of the clock signal CLK. Thus, the levels of input data must not be changed at a rising or falling edge of the clock signal CLK. Therefore, a limited time interval during which the input data levels of the flip-flops must not be changed may exist during a predetermined time before and after the rising or falling edge of the clock signal CLK, and may be referred to as a setup time and a hold time. The setup time refers to a minimum time interval during which the input data levels must not be changed, before the rising edge of the clock signal CLK, and the hold time refers to a minimum time interval during which the input data levels must not be changed, after the rising edge of the clock signal CLK.
However, in the D flip-flop chain circuit of FIG. 2, the clock signal CLK has large loading. Thus, while the input data D0 passes through a large number of D flip-flops, the setup characteristic may be degraded to output data at an undesired level.
In order to solve such a problem, a method illustrated in FIGS. 3A and 3B may be configured.
FIGS. 3A and 3B illustrate another example of the conventional D flip-flop chain circuit.
Referring to FIGS. 3A and 3B, it can be seen that clock signals CLK0 to CLKn−1 are delayed by a predetermined time and then repeated and provided to D flip-flops DFF0 to DFFn−1 forming the D flip-flop chain circuit, respectively. That is, as illustrated in FIG. 3B, the clock signals CLK0 to CLKn−2 are delayed by delay circuits DLY0 to DLYn−2, and provided to the respective D flip-flops DFF0 to DFFn−1. In order to reduce the loading of the clock signals CLK0 to CLKn−2, the D flip-flop chain circuit delays the clock signals CLK0 to CLKn−2 by the predetermined time whenever the data D0 to Dn−1 pass through the respective D flip-flops. However, since an excessively large number of delay circuits DLY0 to DLYn−2 may be required to repeat the clock signals CLK0 to CLKn−2, current consumption may be increased.
FIGS. 4A and 4B illustrate another example of the conventional D flip-flop chain circuit.
In order to solve the problem of the D flip-flop chain circuit illustrated in FIGS. 3A and 3B, the D flip-flops are divided into a plurality of groups, and the repeated clock signal CLK0 is provided to D flip-flop groups after a second D flip-flop group. In this example, the number of delay circuits DLY may be decreased to reduce the area and current consumption. However, when the physical distance between adjacent D flip-flops is not constant, a defect may occur in the setup/hold time.
In order to minimize the occurrence of defect in the setup/hold time depending on the physical distance between adjacent D flip-flops, the data and the clock signal may be set to have the same loading. FIGS. 5A and 5B illustrate this method.
That is, a clock signal repeater illustrated in FIG. 5B may be installed in each of the D flip-flops such that the data and clock signal have the same loading. In FIG. 5B, signal CLKBk is an inverted signal of clock signal CLKk, and signal CLKk+1 is an inverted signal of CLKBk.
In this case, however, a hold margin is not secured for D flip-flops after the second D flip-flop DFF1, and a defect may occur.
FIGS. 6A and 6B are timing diagrams of the D flip-flop chain circuit illustrated in FIG. 5.
FIG. 6A is a timing diagram when the D flip-flop circuit normally operates. Referring to FIG. 6A, it can be seen that input data D (i.e., D0 and Dn) is inputted at a high level H, and high-level data are normally outputted from the respective D flip-flops in response to the clock signal CLK.
On the other hand, referring to FIG. 6B, it can be seen that the logical levels of the data are changed at the second D flip-flop and the following D flip-flops, and the data are outputted at a low level L.
As the D flip-flop chain circuit abnormally operates, the reliability of the test result of the semiconductor apparatus inevitably decreases.
FIG. 7 illustrates another example of the conventional D flip-flop circuit.
The D flip-flop circuit 2 illustrated in FIG. 7 includes an input unit 21, a driving unit 23, an output unit 25, and a reset unit 27.
The D flip-flop circuit of FIG. 7 is different from the D flip-flop circuit of FIG. 1 in that inverters of the driving units 13 and 23 and the output units 15 and 25 are driven in response to different clock signals. That is, the D flip-flop circuit 1 of FIG. 1 drives the driving unit 13 and the output unit 15 using the clock signal CLK and an inverted signal CLKB thereof. On the other hand, the D flip-flop circuit 2 of FIG. 7 drives the driving unit 23 and the output unit 25 using a delayed clock signal CLKD and an inverted signal CLKB thereof.
That is, the time at which data is outputted from the output unit 25 may be delayed to reduce a margin defect caused by the loading of the clock signal CLK, thereby securing a hold margin.
However, when skew occurs due to a difference in delay amount between the clock signal CLK and the delayed clock signal CLKD, a direct current may be generated between an input terminal for the delayed clock signal CLKD and an input terminal for the inverted clock signal CLKB in the inverter during a predetermined time.